| 这是我写的FIR滤波器代码,总觉得不对 |
| 新闻出处：21ic 发布时间：2007-07-21 |
jimmyhua 发布于 2007-6-11 15:11:00
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FIR IS
GENERIC
(
WIDTH : integer := 8
);
PORT
(
CLK,RESET_N : IN STD_LOGIC;
X : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
H : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
Y : INOUT std_logic_vector(2*WIDTH-1 DOWNTO 0)
);
END FIR;
ARCHITECTURE a OF FIR IS
TYPE MEM IS ARRAY(0 TO 7) OF std_logic_vector(2*WIDTH-1 DOWNTO 0);
signal sys_reset : std_logic;
signal c : integer range 0 to 7 :=0;
signal result_sum : std_logic_vector(2*WIDTH-1 DOWNTO 0);
signal result: MEM;
BEGIN
sys_reset <= RESET_N;
result_sum<=Y;
--Y(6)<=result(6);
--Y(5)<=result(5);
--Y(4)<=result(4);
--Y(3)<=result(3);
--Y(2)<=result(1);
--Y(0)<=result(0);
PROCESS (CLK,sys_reset)
BEGIN
IF CLK 'event and CLK='1' THEN
IF sys_reset='0' THEN
Y<="ZZZZZZZZZZZZZZZZ";
--result_sum<="0000000000000000";
END IF;
END IF;
END PROCESS;
PROCESS (CLK)
BEGIN
IF CLK 'event and CLK='1' THEN
result(c)<=X*H;
c<=c+1;
result_sum<=result_sum+result(c);
IF c>=7 THEN
c<=0;
result_sum<="0000000000000000";
END IF;
END IF;
END PROCESS ;
END a;
jimmyhua 发布于 2007-6-11 15:12:00
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Mon Jun 11 15:20:09 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fir -c fir
Info: Found 2 design units, including 1 entities, in source file fir.vhd
Info: Found design unit 1: FIR-a
Info: Found entity 1: FIR
Info: Elaborating entity "fir" for the top level hierarchy
Warning: Reduced register "process0~0" with stuck data_in port to stuck value GND
Warning: Reduced register "process0~1" with stuck data_in port to stuck value GND
Warning: Reduced register "process0~4" with stuck data_in port to stuck value GND
Warning: Reduced register "process0~6" with stuck data_in port to stuck value GND
Warning: Reduced register "process0~8" with stuck data_in port to stuck value GND
Warning: Reduced register "process0~10" with stuck data_in port to stuck value GND
Warning: Reduced register "process0~12" with stuck data_in port to stuck value GND
Warning: Reduced register "process0~14" with stuck data_in port to stuck value GND
Warning: Reduced register "process0~16" with stuck data_in port to stuck value GND
Warning: Reduced register "process0~18" with stuck data_in port to stuck value GND
Warning: Reduced register "process0~20" with stuck data_in port to stuck value GND
Warning: Reduced register "process0~22" with stuck data_in port to stuck value GND
Warning: Reduced register "process0~24" with stuck data_in port to stuck value GND
Warning: Reduced register "process0~26" with stuck data_in port to stuck value GND
Warning: Reduced register "process0~28" with stuck data_in port to stuck value GND
Warning: Reduced register "process0~30" with stuck data_in port to stuck value GND
Warning: Reduced register "Y[14]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "Y[13]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "Y[12]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "Y[11]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "Y[10]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "Y[9]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "Y[8]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "Y[7]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "Y[6]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "Y[5]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "Y[4]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "Y[3]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "Y[2]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "Y[1]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "Y[0]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "Y[15]~reg0" with stuck data_in port to stuck value GND
Warning: Design contains 18 input pin(s) that do not drive logic
Warning: No output dependent on input pin "CLK"
Warning: No output dependent on input pin "RESET_N"
Warning: No output dependent on input pin "X[0]"
Warning: No output dependent on input pin "X[1]"
Warning: No output dependent on input pin "X[2]"
Warning: No output dependent on input pin "X[3]"
Warning: No output dependent on input pin "X[4]"
Warning: No output dependent on input pin "X[5]"
Warning: No output dependent on input pin "X[6]"
Warning: No output dependent on input pin "X[7]"
Warning: No output dependent on input pin "H[0]"
Warning: No output dependent on input pin "H[1]"
Warning: No output dependent on input pin "H[2]"
Warning: No output dependent on input pin "H[3]"
Warning: No output dependent on input pin "H[4]"
Warning: No output dependent on input pin "H[5]"
Warning: No output dependent on input pin "H[6]"
Warning: No output dependent on input pin "H[7]"
Info: Implemented 34 device resources after synthesis - the final resource count might be different
Info: Implemented 18 input pins
Info: Implemented 0 output pins
Info: Implemented 16 bidirectional pins
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 51 warnings
Info: Processing ended: Mon Jun 11 15:20:10 2007
Info: Elapsed time: 00:00:02
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Mon Jun 11 15:20:12 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off fir -c fir
Info: Selected device EP1S10B672C6 for design "fir"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EP1S20B672C6 is compatible
Info: Device EP1S25B672C6 is compatible
Info: No exact pin location assignment(s) for 34 pins of 34 total pins
Info: Pin CLK not assigned to an exact location on the device
Info: Pin RESET_N not assigned to an exact location on the device
Info: Pin X[0] not assigned to an exact location on the device
Info: Pin X[1] not assigned to an exact location on the device
Info: Pin X[2] not assigned to an exact location on the device
Info: Pin X[3] not assigned to an exact location on the device
Info: Pin X[4] not assigned to an exact location on the device
Info: Pin X[5] not assigned to an exact location on the device
Info: Pin X[6] not assigned to an exact location on the device
Info: Pin X[7] not assigned to an exact location on the device
Info: Pin H[0] not assigned to an exact location on the device
Info: Pin H[1] not assigned to an exact location on the device
Info: Pin H[2] not assigned to an exact location on the device
Info: Pin H[3] not assigned to an exact location on the device
Info: Pin H[4] not assigned to an exact location on the device
Info: Pin H[5] not assigned to an exact location on the device
Info: Pin H[6] not assigned to an exact location on the device
Info: Pin H[7] not assigned to an exact location on the device
Info: Pin Y[0] not assigned to an exact location on the device
Info: Pin Y[1] not assigned to an exact location on the device
Info: Pin Y[2] not assigned to an exact location on the device
Info: Pin Y[3] not assigned to an exact location on the device
Info: Pin Y[4] not assigned to an exact location on the device
Info: Pin Y[5] not assigned to an exact location on the device
Info: Pin Y[6] not assigned to an exact location on the device
Info: Pin Y[7] not assigned to an exact location on the device
Info: Pin Y[8] not assigned to an exact location on the device
Info: Pin Y[9] not assigned to an exact location on the device
Info: Pin Y[10] not assigned to an exact location on the device
Info: Pin Y[11] not assigned to an exact location on the device
Info: Pin Y[12] not assigned to an exact location on the device
Info: Pin Y[13] not assigned to an exact location on the device
Info: Pin Y[14] not assigned to an exact location on the device
Info: Pin Y[15] not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1 MHz
Info: Not setting a global tsu requirement
Info: Not setting a global tco requirement
Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Start inferring scan chains for DSP blocks
Info: Inferring scan chains for DSP blocks is complete
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density
Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 34 (unused VREF, 3.30 VCCIO, 18 input, 0 output, 16 bidirectional)
Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 39 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 39 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 43 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used -- 44 pins available
Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 39 pins available
Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 39 pins available
Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 45 pins available
Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 44 pins available
Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 6 pins available
Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 0 pins available
Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 6 pins available
Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 0 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: Following 16 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
Info: Pin Y[0] has a permanently enabled output enable
Info: Pin Y[1] has a permanently enabled output enable
Info: Pin Y[2] has a permanently enabled output enable
Info: Pin Y[3] has a permanently enabled output enable
Info: Pin Y[4] has a permanently enabled output enable
Info: Pin Y[5] has a permanently enabled output enable
Info: Pin Y[6] has a permanently enabled output enable
Info: Pin Y[7] has a permanently enabled output enable
Info: Pin Y[8] has a permanently enabled output enable
Info: Pin Y[9] has a permanently enabled output enable
Info: Pin Y[10] has a permanently enabled output enable
Info: Pin Y[11] has a permanently enabled output enable
Info: Pin Y[12] has a permanently enabled output enable
Info: Pin Y[13] has a permanently enabled output enable
Info: Pin Y[14] has a permanently enabled output enable
Info: Pin Y[15] has a permanently enabled output enable
Warning: Following 16 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Info: Pin Y[0] has GND driving its datain port
Info: Pin Y[1] has GND driving its datain port
Info: Pin Y[2] has GND driving its datain port
Info: Pin Y[3] has GND driving its datain port
Info: Pin Y[4] has GND driving its datain port
Info: Pin Y[5] has GND driving its datain port
Info: Pin Y[6] has GND driving its datain port
Info: Pin Y[7] has GND driving its datain port
Info: Pin Y[8] has GND driving its datain port
Info: Pin Y[9] has GND driving its datain port
Info: Pin Y[10] has GND driving its datain port
Info: Pin Y[11] has GND driving its datain port
Info: Pin Y[12] has GND driving its datain port
Info: Pin Y[13] has GND driving its datain port
Info: Pin Y[14] has GND driving its datain port
Info: Pin Y[15] has GND driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
Info: Processing ended: Mon Jun 11 15:20:22 2007
Info: Elapsed time: 00:00:11
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Mon Jun 11 15:20:24 2007
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off fir -c fir
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Processing ended: Mon Jun 11 15:20:29 2007
Info: Elapsed time: 00:00:05
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Mon Jun 11 15:20:30 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fir -c fir --timing_analysis_only
Warning: No paths found for timing analysis
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Mon Jun 11 15:20:31 2007
Info: Elapsed time: 00:00:01
Info: Quartus II Full Compilation was successful. 0 errors, 54 warnings
xiao_mm 发布于 2007-7-19 10:53:00
不管warning，仿镇一下看看
yanxuyuan 发布于 2007-7-21 16:59:00
这个程序没有错误吗 总感觉你的代码本身就有语法错误
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